CPU Architecture & FDE Simulator

Interactive Fetch–Decode–Execute cycle, Registers, Buses, 16-Cell RAM, Cache Hierarchy, Multi-Core & Pipelining

1. CPU & FDE Sim 2. Cache, Cores & Pipeline
Starter Programs:
Fetch / Address Bus Decode / Control Bus Execute / Data Bus ALU & Branch

Program Editor

One instruction per line (0–15)

✓ Valid ASM

Input Stream (for INP)

Comma or space-separated integers

0 waiting

Output Tape (from OUT)

Values emitted by AC during execution

No output emitted yet...
Clock Speed: 1.5x
Instr Completed: 0 Micro-Steps: 0
1. FETCH 2. DECODE 3. EXECUTE
READY IDLE
Program assembled into RAM. Click Step Micro-Op (FDE) to watch how the Program Counter (PC) begins the Fetch phase.

CPU Internal Registers

Tracks current & before-last-write values
PC — Program Counter

Holds RAM address of the next instruction

Current
0
Before last write
No write recorded
MAR — Memory Address Reg

Drives target address onto the Address Bus

Current
—
Before last write
No write recorded
MDR — Memory Data Reg

Buffers instruction/data sent over Data Bus

Current
—
Before last write
No write recorded
IR — Instruction Register

Holds current instruction being decoded

Current
—
Before last write
No write recorded
AC — Accumulator Register

Primary working register for ALU arithmetic (ADD, SUB), loads/stores (LDA, STA), and I/O (INP, OUT)

Current Value
0
Before last write
No write recorded
Control Unit (CU) IDLE
Awaiting instruction in IR
ALU & Status Flags IDLE
Z (AC=0): 1 P (AC≥0): 1 N (AC<0): 0

System Buses (CPU ↔ RAM Interconnect)

Live signal conduits
Address Bus (MAR → RAM) IDLE
Data Bus (MDR ↔ RAM) IDLE
Control Bus (CU → RAM) IDLE

Main Memory (RAM — 16 Cells)

Shared Von Neumann memory for instructions & data. Click any cell to edit live.

← PC (Next Instruction) ← MAR (Active Target)
Part 2 • Companion Hardware Labs

Beyond One Instruction: Memory Hierarchy, Multi-Core & Pipelining

Explore how modern processors overcome the Von Neumann bottleneck using inclusive LRU caches, parallel cores, and instruction pipelines.

Activity 1

Memory Hierarchy — Follow a Read (Fully Associative Inclusive Cache with LRU)

Checking starts at L1 (+1 cost) → L2 (+3 cost) → L3 (+8 cost) → RAM (+25 cost) only on a MISS. A HIT supplies the value immediately, moves the entry to the MRU (Most Recently Used) front of each checked cache, and copies it into any cache level that missed. Inclusive eviction rule: When a larger cache evicts its LRU entry, any copy in smaller caches is removed too.

Read Address:
Click any address [0]–[7] above to trace a memory read through L1, L2, L3, and RAM.
Last Read Cost
0
Total Cost
0
Cache Hit Rate
0%

L1 CACHE (2 Slots)

Lookup Cost: +1 cycle

IDLE
← MRU (Newest) LRU (Oldest) →

L2 CACHE (4 Slots)

Lookup Cost: +3 cycles

IDLE
← MRU (Newest) LRU (Oldest) →

L3 CACHE (6 Slots)

Lookup Cost: +8 cycles

IDLE
← MRU (Newest) LRU (Oldest) →

MAIN MEMORY (RAM)

Lookup Cost: +25 cycles

IDLE
8 Backing Store Addresses [0]–[7]
CPU Registers & SRAM Cache Fastest, smallest storage built directly inside the CPU die. Volatile; holds immediate operands and recently accessed lines.
Main Memory (DRAM) Holds active programs and data currently running. Volatile (clears on power off), much larger capacity, higher latency (+25).
ROM / Non-Volatile Firmware Read-Only Memory retains bootloaders (BIOS/UEFI) without power so the CPU has initial instructions upon startup.
Activity 2

Independent Cores — Share the Work (1-Core vs. 2-Core Machine & Where a GPU Fits)

Both machines square the same six independent inputs: 2, 3, 4, 5, 6, 7 (producing 4, 9, 16, 25, 36, 49). Each task takes 2 work units on one core. Watch how independent tasks scale across cores.

1-Core Machine (Sequential)

1 core executes all 6 tasks one after another (12 steps total)

Step 0 / 12
Core 0: Ready

2-Core Machine (Parallel)

Core 0 & Core 1 work simultaneously (Finishes in 6 steps!)

Step 0 / 6
Core 0: Ready
Core 1: Ready

Where a GPU Fits (SIMT / Massive Data Parallelism)

While a CPU has a handful of complex cores optimized for sequential branching and low latency, a GPU contains hundreds or thousands of simpler ALUs executing the same instruction across many data elements simultaneously. Because squaring 2, 3, 4, 5, 6, 7 has zero data dependencies between elements, a GPU dispatches all 6 elements in parallel and finishes the entire batch in just 2 steps!

6-Lane GPU SIMD
All 6 Done in 2 Steps
Activity 3

Four-Stage Instruction Pipeline (Sequential vs. 4-Stage Pipelined Execution)

Compare running 5 instructions (LDA 5, ADD 6, STA 7, OUT, HLT) across 4 hardware stages: F (Fetch), D (Decode), E (Execute), and W (Write-back). Without pipelining takes 20 clock cycles; overlapping stages in a 4-stage pipeline finishes all 5 instructions in 8 clock cycles!

Current Clock Cycle Cycle 0 / 20
Unpipelined Completed 0 / 5 (20 cyc)
Pipelined Completed 0 / 5 (8 cyc)

Without Pipelining (1 Instruction Active at a Time — 20 Cycles)

Waiting...

With 4-Stage Pipelining (Overlapped Stages — Finishes in 8 Cycles!)

Waiting...